by Luke Hickman
February 9, 2018
The development of smaller, more advanced process nodes has slowed as the semiconductor machinery industry has struggled to produce the technology expected to improve the costs of manufacturing smaller nodes. However, many producers now seem to be ready to move forward.
Semiconductor makers (particularly those that produce logic and memory integrated circuits) rely on the timely availability of new wafer processing equipment capable of fitting more transistors on a chip of a given size at an acceptable cost to maintain new product introductions. The size of transistors a machine is capable of producing on a chip is referred to as the process node. In 2017, 10 nm was the smallest node in mass production. TSMC’s 10 nm technology was first utilized in the Apple A10X chips in 2017 that powered the second-generation iPad Pro tablets, while Samsung Electronics began mass production of System-on-Chip (SoC) products on 10 nm FinFET process technology at the end of November 2017. Intel’s 10 nm technology is expected to be introduced sometime in 2018 (once upon a time, this introduction was anticipated for 2015). GlobalFoundries, another leading semiconductor manufacturer, appears to be skipping 10 nm and aiming for mass production of 7 nm technology in 2019.
Due to delays in the development of EUV (extreme ultraviolet) lithography semiconductor firms have implemented a variety of advanced immersion techniques to extend the capabilities of current DUV (deep ultraviolet) technology. The double-patterning process became common at the 20 nm node. By splitting a layer pattern between two lithography-and-etch passes, companies can effectively manufacture transistors on a smaller scale. Triple-patterning is sometimes used in parts of 14 nm production, and as node sizes get smaller, more advanced multiple-patterning methods will become necessary. Another commonly used technique is immersion lithography, which allows improved resolution in the etching process by replacing the air gap between the final lens and the wafer with a liquid (usually water).
Leading semiconductor manufacturers who have outlined plans to integrate EUV technology plan to have EUV systems up and running no earlier than 2019, with others aiming for 2020. In the meantime, semiconductor manufacturers will increasingly employ multiple-patterning with existing lithography technologies to maintain new product introductions beyond the 14 nm node, even though multiple-patterning results in higher production costs per semiconductor. For instance, GlobalFoundries is planning on using existing DUV techniques for the initial production of its 7 nm technologies, but hopes to phase in EUV tools as they become available.
For more insights into the US semiconductor industry, see Semiconductors: United States, a report recently released by the Freedonia Focus Reports division of The Freedonia Group. This report forecasts to 2021 US semiconductor shipments in nominal US dollars at the manufacturer level. Total shipments are segmented by product in terms of:
For more insights into the US semiconductor machinery market, see Semiconductor Machinery: United States, a report recently released by the Freedonia Focus Reports division of The Freedonia Group. This report forecasts to 2021 US semiconductor machinery demand and shipments in nominal US dollars at the manufacturer level. Total demand is segmented by product in terms of:
Other related Freedonia Focus Reports include:
Luke Hickman is a Research Analyst for Freedonia Focus Reports. He holds a degree in economics, and his experience as an analyst covers multiple industries.
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